A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management

Harold Pilo, Vaidyanathan Ramadurai, Geordie Braceras, John Gabric, Steve Lamphier, Yue Tan. A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management. In 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008. pages 378-379, IEEE, 2008. [doi]

@inproceedings{PiloRBGLT08,
  title = {A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management},
  author = {Harold Pilo and Vaidyanathan Ramadurai and Geordie Braceras and John Gabric and Steve Lamphier and Yue Tan},
  year = {2008},
  doi = {10.1109/ISSCC.2008.4523215},
  url = {http://dx.doi.org/10.1109/ISSCC.2008.4523215},
  researchr = {https://researchr.org/publication/PiloRBGLT08},
  cites = {0},
  citedby = {0},
  pages = {378-379},
  booktitle = {2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008},
  publisher = {IEEE},
  isbn = {978-1-4244-2010-0},
}