VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Irith Pomeranz, Sudhakar M. Reddy. VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. In 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India. pages 250-255, IEEE Computer Society, 1999. [doi]

This author has not been identified. Look up 'Irith Pomeranz' in GoogleThis author has not been identified. Look up 'Sudhakar M. Reddy' in Google

runs on WebDSL