VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits

Irith Pomeranz, Sudhakar M. Reddy. VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. In 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India. pages 250-255, IEEE Computer Society, 1999. [doi]

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