Logic BIST Architecture for System-Level Test and Diagnosis

Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, Feifei Zhao, Laung-Terng Wang. Logic BIST Architecture for System-Level Test and Diagnosis. In Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan. pages 21-26, IEEE Computer Society, 2009. [doi]

@inproceedings{QianWYZJLZMLCWYYZW09,
  title = {Logic BIST Architecture for System-Level Test and Diagnosis},
  author = {Jun Qian and Xingang Wang and Qinfu Yang and Fei Zhuang and Junbo Jia and Xiangfeng Li and Yuan Zuo and Jayanth Mekkoth and Jinsong Liu and Hao-Jan Chao and Shianling Wu and Huafeng Yang and Lizhen Yu and Feifei Zhao and Laung-Terng Wang},
  year = {2009},
  doi = {10.1109/ATS.2009.34},
  url = {http://doi.ieeecomputersociety.org/10.1109/ATS.2009.34},
  tags = {architecture, testing, logic},
  researchr = {https://researchr.org/publication/QianWYZJLZMLCWYYZW09},
  cites = {0},
  citedby = {0},
  pages = {21-26},
  booktitle = {Proceedings of the Eighteentgh Asian Test Symposium, ATS 2009, 23-26 November 2009, Taichung, Taiwan},
  publisher = {IEEE Computer Society},
  isbn = {978-0-7695-3864-8},
}