A low-power and high-speed parallel binary comparator based on inter-stage modified binary tree structure and power-delay improved cell elements - researchr publication

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M. Rahimi, M. B. Ghaznavi-Ghoushchi. A low-power and high-speed parallel binary comparator based on inter-stage modified binary tree structure and power-delay improved cell elements. Microelectronics Journal, 88:37-46, 2019. [doi]

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