Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen. Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. In 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France. pages 604-609, IEEE Computer Society, 2004. [doi]
@inproceedings{RanjanVASVG04,
title = {Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models},
author = {Mukesh Ranjan and Wim Verhaegen and Anuradha Agarwal and Hemanth Sampath and Ranga Vemuri and Georges G. E. Gielen},
year = {2004},
url = {http://csdl.computer.org/comp/proceedings/date/2004/2085/01/208510604abs.htm},
tags = {layout, e-science, compiler, context-aware},
researchr = {https://researchr.org/publication/RanjanVASVG04},
cites = {0},
citedby = {0},
pages = {604-609},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France},
publisher = {IEEE Computer Society},
isbn = {0-7695-2085-5},
}