The following publications are possibly variants of this publication:
- Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit SynthesisHuiying Yang, Ranga Vemuri. vlsid 2007: 201-206 [doi]
- A high level language for pre-layout extraction in parasite-aware analog circuit synthesisRaoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri. glvlsi 2004: 271-276 [doi]
- A layout-aware analog synthesis procedure inclusive of dynamic module geometry selectionAlmitra Pradhan, Ranga Vemuri. glvlsi 2008: 159-162 [doi]
- Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog CircuitsAlmitra Pradhan, Ranga Vemuri. vlsid 2009: 131-136 [doi]
- Fast and accurate parasitic capacitance models for layout-awareAnuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri. dac 2004: 145-150 [doi]
- Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic CornersAnuradha Agarwal, Ranga Vemuri. iccd 2005: 444-452 [doi]