A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping

Sitansusekhar Roymohapatra, Ganesh R. Gore, Akanksha Yadav, Mahesh B. Patil, Krishnan S. Rengarajan, Subramanian S. Iyer, Maryam Shojaei Baghini. A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping. IEEE Trans. on CAD of Integrated Circuits and Systems, 39(5):1073-1083, 2020. [doi]

@article{RoymohapatraGYP20,
  title = {A Novel Hierarchical Circuit LUT Model for SOI Technology for Rapid Prototyping},
  author = {Sitansusekhar Roymohapatra and Ganesh R. Gore and Akanksha Yadav and Mahesh B. Patil and Krishnan S. Rengarajan and Subramanian S. Iyer and Maryam Shojaei Baghini},
  year = {2020},
  doi = {10.1109/TCAD.2019.2907879},
  url = {https://doi.org/10.1109/TCAD.2019.2907879},
  researchr = {https://researchr.org/publication/RoymohapatraGYP20},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {39},
  number = {5},
  pages = {1073-1083},
}