The following publications are possibly variants of this publication:
- A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processorCheolmin Park, Roy Badeau, Larry Biro, Jonathan Chang, Tejpal Singh, Jim Vash, Bo Wang, Tom Wang. isscc 2010: 180-181 [doi]
- A 45 nm 8-Core Enterprise Xeon¯ ProcessorStefan Rusu, Simon Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora. jssc, 45(1):7-14, 2010. [doi]
- Power reduction techniques for an 8-core xeon® processorStefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora. esscirc 2009: 340-343 [doi]
- A 22 nm 15-Core Enterprise Xeon® Processor FamilyStefan Rusu, Harry Muljono, David Ayers, Simon Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang. jssc, 50(1):35-48, 2015. [doi]
- 5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor familyStefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang. isscc 2014: 102-103 [doi]