Evaluation of low-energy and high-performance processor using variable stages pipeline technique

Takahiro Sasaki, Yuji Ichikawa, Tetsuo Hironaka, Toshiaki Kitamura, Toshio Kondo. Evaluation of low-energy and high-performance processor using variable stages pipeline technique. IET Computers & Digital Techniques, 2(3):230-238, 2008. [doi]

Authors

Takahiro Sasaki

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Yuji Ichikawa

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Tetsuo Hironaka

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Toshiaki Kitamura

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Toshio Kondo

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