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Takahiro Sasaki, Yuji Ichikawa, Tetsuo Hironaka, Toshiaki Kitamura, Toshio Kondo. Evaluation of low-energy and high-performance processor using variable stages pipeline technique. IET Computers & Digital Techniques, 2(3):230-238, 2008. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Design and evaluation of variable stages pipeline processor with low-energy techniquesT. Nakabayashi, T. Sasaki, I. K. Ohno, T. Kondo. iet-cdt, 6(1):43-49, 2012. [doi]
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