4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]

Takahide Sato, Shigetaka Takagi, Nobuo Fujii, Yasuyuki Hashimoto, Kohji Sakata, Hirovuki Okada. 4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]. In Michiel Steyaert, C. L. Claeys, editors, 33rd European Solid-State Circuits Conference, ESSCIRC 2004, Leuven, Belgium, September 21-23, 2004. pages 347-350, IEEE, 2004. [doi]

@inproceedings{SatoTFHSO04,
  title = {4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]},
  author = {Takahide Sato and Shigetaka Takagi and Nobuo Fujii and Yasuyuki Hashimoto and Kohji Sakata and Hirovuki Okada},
  year = {2004},
  doi = {10.1109/ESSCIR.2004.1356689},
  url = {https://doi.org/10.1109/ESSCIR.2004.1356689},
  researchr = {https://researchr.org/publication/SatoTFHSO04},
  cites = {0},
  citedby = {0},
  pages = {347-350},
  booktitle = {33rd European Solid-State Circuits Conference, ESSCIRC 2004, Leuven, Belgium, September 21-23, 2004},
  editor = {Michiel Steyaert and C. L. Claeys},
  publisher = {IEEE},
}