John Y. Sayah, Rajesh Gupta, Deepak D. Sherlekar, Philip S. Honsinger, Jitendra M. Apte, S. Wayne Bollinger, Hai Hsia Chen, Sumit Dasgupta, Edward P. Hsieh, Andrew D. Huber, Edward J. Hughes, Zahi M. Kurzum, Vasant B. Rao, Thepthai Tabtieng, Vigen Valijan, David Y. Yang. Design planning for high-performance ASICs. IBM Journal of Research and Development, 40(4):431-452, 1996. [doi]
@article{SayahGSHABCDHHHKRTVY96,
title = {Design planning for high-performance ASICs},
author = {John Y. Sayah and Rajesh Gupta and Deepak D. Sherlekar and Philip S. Honsinger and Jitendra M. Apte and S. Wayne Bollinger and Hai Hsia Chen and Sumit Dasgupta and Edward P. Hsieh and Andrew D. Huber and Edward J. Hughes and Zahi M. Kurzum and Vasant B. Rao and Thepthai Tabtieng and Vigen Valijan and David Y. Yang},
year = {1996},
doi = {10.1147/rd.404.0431},
url = {http://dx.doi.org/10.1147/rd.404.0431},
tags = {design},
researchr = {https://researchr.org/publication/SayahGSHABCDHHHKRTVY96},
cites = {0},
citedby = {0},
journal = {IBM Journal of Research and Development},
volume = {40},
number = {4},
pages = {431-452},
}