Stanley Schuster, Peter W. Cook. Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. J. Solid-State Circuits, 38(4):622-630, 2003. [doi]
@article{SchusterC03,
title = {Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz},
author = {Stanley Schuster and Peter W. Cook},
year = {2003},
doi = {10.1109/JSSC.2003.809512},
url = {https://doi.org/10.1109/JSSC.2003.809512},
researchr = {https://researchr.org/publication/SchusterC03},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {38},
number = {4},
pages = {622-630},
}