Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz - researchr publication references

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Stanley Schuster, Peter W. Cook. Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. J. Solid-State Circuits, 38(4):622-630, 2003. [doi]

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