Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz

Stanley Schuster, Peter W. Cook. Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. J. Solid-State Circuits, 38(4):622-630, 2003. [doi]

Abstract

Abstract is missing.