The following publications are possibly variants of this publication:
- User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesisAnirban Sengupta, Saumya Bhadauria. isqed 2015: 289-292 [doi]
- Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budgetAnirban Sengupta, Reza Sedaghat. mr, 55(6):990-1004, 2015. [doi]
- Simultaneous exploration of optimal datapath and loop based high level transformation during area-delay tradeoff in architectural synthesis using swarm intelligenceAnirban Sengupta, Vipul Kumar Mishra. kes, 19(1):47-61, 2015. [doi]
- Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay BudgetAnirban Sengupta, Saumya Bhadauria. cit 2014: 345-350 [doi]
- Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesisAnirban Sengupta, Saumya Bhadauria. eswa, 42(10):4719-4732, 2015. [doi]
- PSO based exploration of multi-phase encryption based secured image processing filter hardware IP core datapath during high level synthesisAditya Anshul, Anirban Sengupta. eswa, 223:119927, August 2023. [doi]
- Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processorsDeepak Kachave, Anirban Sengupta. mr, 60:141-152, 2016. [doi]
- Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level SynthesisAnirban Sengupta, Saumya Bhadauria. glvlsi 2015: 167-172 [doi]
- GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesisPallabi Sarkar, Anirban Sengupta, Mrinal Kanti Naskar. ccece 2015: 75-80 [doi]
- Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computingAnirban Sengupta, Saumya Bhadauria. aes, 82:14-24, 2015. [doi]
- Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level SynthesisAnirban Sengupta, Deepak Kachave. isvlsi 2016: 75-80 [doi]