External Links

Cite Key

Statistics

  • References: 0
  • Cited by: 0
  • Reviews: 0
  • Bibliographies: 0

PDF

Researchr

Researchr is a web site for finding, collecting, sharing, and reviewing scientific publications, for researchers by researchers.

Sign up for an account to create a profile with publication list, tag and review your related work, and share bibliographies with your co-authors.

Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms

Kunwar Singh, Aman Jain, Aviral Mittal, Vinay Yadav, Atul Anshuman Singh, Anmoll Kumar Jain, Maneesha Gupta. Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms. Integration, 60:25-38, 2018. [doi]

Authors

Kunwar Singh

This author has not been identified. Look up 'Kunwar Singh' in Google

Aman Jain

This author has not been identified. Look up 'Aman Jain' in Google

Aviral Mittal

This author has not been identified. Look up 'Aviral Mittal' in Google

Vinay Yadav

This author has not been identified. Look up 'Vinay Yadav' in Google

Atul Anshuman Singh

This author has not been identified. Look up 'Atul Anshuman Singh' in Google

Anmoll Kumar Jain

This author has not been identified. Look up 'Anmoll Kumar Jain' in Google

Maneesha Gupta

This author has not been identified. Look up 'Maneesha Gupta' in Google
runs on