Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms - researchr publication

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Kunwar Singh, Aman Jain, Aviral Mittal, Vinay Yadav, Atul Anshuman Singh, Anmoll Kumar Jain, Maneesha Gupta. Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms. Integration, 60:25-38, 2018. [doi]

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