Kunwar Singh, Aman Jain, Aviral Mittal, Vinay Yadav, Atul Anshuman Singh, Anmoll Kumar Jain, Maneesha Gupta. Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms. Integration, 60:25-38, 2018. [doi]
@article{SinghJMYSJG18,
title = {Optimum transistor sizing of CMOS logic circuits using logical effort theory and evolutionary algorithms},
author = {Kunwar Singh and Aman Jain and Aviral Mittal and Vinay Yadav and Atul Anshuman Singh and Anmoll Kumar Jain and Maneesha Gupta},
year = {2018},
doi = {10.1016/j.vlsi.2017.08.003},
url = {https://doi.org/10.1016/j.vlsi.2017.08.003},
researchr = {https://researchr.org/publication/SinghJMYSJG18},
cites = {0},
citedby = {0},
journal = {Integration},
volume = {60},
pages = {25-38},
}