The following publications are possibly variants of this publication:
- Integration of Clock Skew and Register Delays into a Retiming AlgorithmTolga Soyata, Eby G. Friedman, James H. Mulligan Jr.. iscas 1993: 1483-1486
- Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register DelayTolga Soyata, Eby G. Friedman, James H. Mulligan Jr.. iscas 1995: 1748-1751
- Incorporating interconnect, register, and clock distribution delays into the retiming processTolga Soyata, Eby G. Friedman, James H. Mulligan Jr.. tcad, 16(1):105-120, 1997. [doi]
- Maximizing Performance by Retiming and Clock Skew SchedulingXun Liu, Marios C. Papaefthymiou, Eby G. Friedman. dac 1999: 231-236 [doi]