Anastasia Spyrou, Dimitris Bakalis, Haridimos T. Vergos. Efficient architectures for modulo 2n-1 squares. In 16th International Conference on Digital Signal Processing, DSP 2009, Santorini, Greece, July 5-7, 2009. pages 1-6, IEEE, 2009. [doi]
@inproceedings{SpyrouBV09,
title = {Efficient architectures for modulo 2n-1 squares},
author = {Anastasia Spyrou and Dimitris Bakalis and Haridimos T. Vergos},
year = {2009},
doi = {10.1109/ICDSP.2009.5201088},
url = {https://doi.org/10.1109/ICDSP.2009.5201088},
researchr = {https://researchr.org/publication/SpyrouBV09},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {16th International Conference on Digital Signal Processing, DSP 2009, Santorini, Greece, July 5-7, 2009},
publisher = {IEEE},
isbn = {978-1-4244-3298-1},
}