The following publications are possibly variants of this publication:
- High-Speed Parallel-Prefix Modulo 2n-1 AddersLampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, John Kalamatianos. TC, 49(7):673-680, 2000. [doi]
- Efficient modulo 2:::n:::±1 squarersDimitris Bakalis, Haridimos T. Vergos, A. Spyrou. integration, 44(3):163-174, 2011. [doi]
- Efficient modulo 2:::n:::+1 adder architecturesHaridimos T. Vergos, Costas Efstathiou. integration, 42(2):149-157, 2009. [doi]