The following publications are possibly variants of this publication:
- A 65nm 2-Billion-Transistor Quad-Core Itanium® ProcessorBlaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles. isscc 2008: 92-93 [doi]
- A 32 nm, 3.1 Billion Transistor, 12 Wide Issue Itanium® Processor for Mission-Critical ServersReid J. Riedlinger, Ron Arnold, Larry Biro, William J. Bowhill, Jason Crop, Kevin Duda, Eric S. Fetzer, Olivier Franza, Tom Grutkowski, Casey Little, Charles Morganti, Gary Moyer, Ashley Munch, Mahalingam Nagarajan, Cheolmin Park, Christopher Poirier, Bill Repasky, Edi Roytman, Tejpal Singh, Matthew W. Stefaniw. jssc, 47(1):177-193, 2012. [doi]
- Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® ProcessorDan Krueger, Erin Francom, Jack Langsdorf. isscc 2008: 94-95 [doi]
- Dynamic frequency-switching clock system on a quad-core Itanium® processorAndrew Allen, Jay Desai, Frank Verdico, Ferd Anderson, David Mulvihill, Dan Krueger. isscc 2009: 62-63 [doi]