The following publications are possibly variants of this publication:
- A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stackingMitsuko Saito, Noriyuki Miura, Tadahiro Kuroda. isscc 2010: 440-441 [doi]
- 2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory StackingMitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda. jssc, 45(1):134-141, 2010. [doi]
- 47% power reduction and 91% area reduction in inductive-coupling programmable bus for NAND flash memory stackingMitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda. cicc 2009: 449-452 [doi]
- 47% Power Reduction and 91% Area Reduction in Inductive-Coupling Programmable Bus for NAND Flash Memory StackingMitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda. tcas, 57-I(9):2269-2278, 2010. [doi]
- 2 0.9pJ/b/chip 1coil/channel ThruChip interface with coupled-resonator-based CDR for NAND Flash memory stackingNoriyuki Miura, Yasuhiro Take, Mitsuko Saito, Yoichi Yoshida, Tadahiro Kuroda. isscc 2011: 490-492 [doi]