Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada. A 500 MHz, 32 bit, 0.4 /spl mu/m CMOS RISC processor. J. Solid-State Circuits, 29(12):1464-1473, December 1994. [doi]
@article{SuzukiYNINIHGIKAOOYY94,
title = {A 500 MHz, 32 bit, 0.4 /spl mu/m CMOS RISC processor},
author = {Kazumasa Suzuki and Masakazu Yamashina and Takashi Nakayama and Masanori Izumikawa and Masahiro Nomura and Hiroyuki Igura and Hideki Heiuchi and Junichi Goto and Toshiaki Inoue and Youichi Koseki and Hitoshi Abiko and Kazuhiro Okabe and Atsuki Ono and Youich Yano and Hachiro Yamada},
year = {1994},
month = {December},
doi = {10.1109/4.340419},
url = {https://doi.org/10.1109/4.340419},
researchr = {https://researchr.org/publication/SuzukiYNINIHGIKAOOYY94},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {29},
number = {12},
pages = {1464-1473},
}