Daisaburo Takashima, Hiroaki Nakano. A cell transistor scalable DRAM array architecture. J. Solid-State Circuits, 37(5):587-591, 2002. [doi]
@article{TakashimaN02,
title = {A cell transistor scalable DRAM array architecture},
author = {Daisaburo Takashima and Hiroaki Nakano},
year = {2002},
doi = {10.1109/4.997851},
url = {https://doi.org/10.1109/4.997851},
researchr = {https://researchr.org/publication/TakashimaN02},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {37},
number = {5},
pages = {587-591},
}