Reversible Logic Synthesis of Half, Full and Parallel Subtractors - researchr publication authors

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Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia. Reversible Logic Synthesis of Half, Full and Parallel Subtractors. In Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic, editors, Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005. pages 165-181, CSREA Press, 2005.

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