Reversible Logic Synthesis of Half, Full and Parallel Subtractors - researchr publication related

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Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia. Reversible Logic Synthesis of Half, Full and Parallel Subtractors. In Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic, editors, Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005. pages 165-181, CSREA Press, 2005.

The following publications are possibly variants of this publication:

A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-SubtractorHimanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia. csreaESA 2005: 60-68

The New BCD Subtractor and Its Reversible Logic ImplementationHimanshu Thapliyal, M. B. Srinivas. APCSAC 2006: 466-472 [doi]

Efficient Reversible Logic Design of BCD SubtractorsHimanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas. tcos, 3:99-121, 2009. [doi]

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