Reversible Logic Synthesis of Half, Full and Parallel Subtractors - researchr publication

researchr

You are not signed in
Sign in
Sign up

Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia. Reversible Logic Synthesis of Half, Full and Parallel Subtractors. In Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic, editors, Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005. pages 165-181, CSREA Press, 2005.

Abstract is missing.

runs on WebDSL