A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs - researchr publication

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Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia. A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs. In Hamid R. Arabnia, Mary Mehrnoosh Eshaghian-Wilner, editors, Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, CDES 2006, Las Vegas, Nevada, USA, June 26-29, 2006. pages 36-38, CSREA Press, 2006.

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