Abstract is missing.
- On the Management of Object InterrelationshipsMartin Uhl, Werner Held. 3-9
- A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic MinimizationSirzat Kahramanli, Suleyman Tosun. 10-16
- RHT: A Context-Based Return Address PredictorMohamed M. Zahran, Manoj Franklin. 17-23
- Round-Robin Arbiter DesignJinming Ge. 24-28
- Using Task Recomputation During Application Mapping in Parallel Embedded ArchitecturesSuleyman Tosun, Mahmut T. Kandemir, Hakduran Koc. 29-35
- A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICsHimanshu Thapliyal, Vishal Verma, Hamid R. Arabnia. 36-38
- Modeling and Realization of the Floating Point Inverse Square Root, Square Root, and Division unit (fP ISD) Using VHDL and FPGAsJaafar Alghazo. 39-45
- An Algorithm for Yield Improvement via Local Positioning and ResizingVazgen Karapetyan. 46-49
- ANN-Based Spiral Inductor Parameter Extraction and Layout Re-DesignAbby A. Ilumoka, Yeonbum Park. 50-56
- Crosstalk at the Dynamic Node of Domino CMOS CircuitsWaleed Al-Assadi, Vipin Sharma, Pavankumar Chandrasekhar. 57-63
- Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic ImplementationHimanshu Thapliyal, Hamid R. Arabnia. 64-69
- A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and ApplicationsHimanshu Thapliyal, Hamid R. Arabnia. 70-76
- Survey and Evaluation of Low-Power Flip-FlopsAhmed Sayed, Hussain Al-Asaad. 77-83
- The Impact of Cache Organization in Optimizing Microprocessor Power ConsumptionNagm Mohamed, Nazeih Botros, Wei Zhang. 84-90
- Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop BufferBin-Hua Tein, I-Wei Wu, Chung-Ping Chung. 91-96
- Zero Detect-Based Low Power Registers File AccessMoises Zarate, Oscar Camacho Nieto, Luis Villa Vargas, Osvaldo Espinosa. 97-100
- Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin GatesAmin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury. 101-106
- Communicating Distributed H systems with Simple Splicing RulesKamala Krithivasan, Prahladh Harsha, Muralidhar Talupur. 107-111
- Design of Low Power 4-Tap 8-Bit Adiabatic FIR FilterArun N. Chandorkar, Gurvinder Singh. 112-117
- Protein Secondary Structure Prediction Accuracy versus Reduction MethodsSaad Osman Abdalla Subair, Safaai Deris. 118-124
- Simulation of a Turing Machine using EndoII Splicing RulesKamala Kritihivasan, Anshu Bhatia, T. S. Chandra. 125-129
- Novel NAND and AND Gate Using DNA Ligation and Two Transistors ImplementationsHimanshu Thapliyal, A. Rameshwar, Rajnish Bajpai, Hamid R. Arabnia. 130-134
- Semi-Contiguous Memory Allocation for Efficient Sequential-AccessElias G. Khalaf, Ralph Tucci. 135-140
- Reducing Memory References for FFT CalculationAyman Elnaggar, Mokhtar Aboelaze. 141-145
- Autonomous Instruction Memory Equipped with Dynamic Branch Handling CapabilityHui-Chin Yang, Chung-Ping Chung. 146-152
- Bandwidth-Friendly Cache HierarchyAnasua Bhowmik, Mohamed M. Zahran. 153-159
- Bio-Inspired Celluar Systems With Cyclic Metamorphic MemoryGabriel Dragffy, Mohammad Samie, Ebrahim Farjah. 160-168
- An FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware EmulationYajuvendra Nagaonkar, Mark L. Manwaring. 169-174
- New DSP Benchmark based on Selectable Mode Vocoder (SMV)Erh-Wen Hu, Cyril Ku, Andrew Russo, Bogong Su, Jian Wang. 175-181
- Improving the System Performance by a Dynamic File Prediction ModelTsozen Yeh, Joseph Arul, Kuo-Hsin Tien, I-Fan Chen, Jia-Shian Wu. 182-188
- A Generic Framework for Rapid Prototyping of System-on-Chip DesignsDmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich. 189-195
- Hybrid Error-Detection Approach with No Detection Latency for High-Performance MicroprocessorsYung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin. 196-202
- A New Processor Architecture with a New Program Driving MethodXiaobo Li, Ke Luo, Xiangdong Cui, Lalin Jiang, Xiaoqiang Ni, Chiyuan Ma, Jingfei Jiang, Huiping Zhou, Zhou Zhou. 203-206
- A Configuration Concept for a Massively Parallel FPGA ArchitectureSandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler. 207-212
- CMOL FPGA circuitsDmitri B. Strukov, Konstantin Likharev. 213-219
- Hierarchical Multi-Scale Architectures with Spin WavesMary Mehrnoosh Eshaghian-Wilner, Alexander Khitun, Shiva Navab, Kang L. Wang. 220-226
- Towards a Nanoscale Artificial CortexAlice C. Parker, Aaron K. Friesz, Afshaneh Pakdaman. 227-241
- Graph Formations of Partial-Order Multiple-Sequence Alignments Using Nano and Micro-Scale Reconfigurable MeshesMary Mehrnoosh Eshaghian-Wilner, Ling Lau, Shiva Navab, David Shen. 242-250
- Compilation for Future Nanocomputer ArchitecturesThomas P. Way. 251-257
- MolML: An Abstract Scripting Language for Assembly of Mechanical Nanocomputer ArchitecturesBryan W. Wagner, Thomas P. Way. 258-264
- Teraflop Computing for NanoscienceYang Wang, G. M. Stocks, Aurelian Rusanu, D. M. C. Nicholson, Markus Eisenbach, J. S. Faulkner. 265-271
- A Computer Algebra Algorithm for the Symbolic Solution of a Problem involving the diffusion of adatoms on a Circular Wafer when sculpting a Nanopore with an Ion BeamEsteban García Tamayo, Juan Ospina. 272-280
- Novel Complex Vauled Neural NetworksNarendra Ahuja, Garimella Rama Murthy. 281-286
- Integrity and Integration Issues for Nano-Tube Based Interconnect SystemsTulin Mangir. 287