Parity prediction synthesis for nano-electronic gate designs

D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich. Parity prediction synthesis for nano-electronic gate designs. In Ron Press, Erik H. Volkerink, editors, 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010. pages 820, IEEE, 2010. [doi]

Authors

D. A. Tran

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Arnaud Virazel

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Alberto Bosio

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Luigi Dilillo

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Patrick Girard

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Serge Pravossoudovitch

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Hans-Joachim Wunderlich

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