D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich. Parity prediction synthesis for nano-electronic gate designs. In Ron Press, Erik H. Volkerink, editors, 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010. pages 820, IEEE, 2010. [doi]
@inproceedings{TranVBDGPW10,
title = {Parity prediction synthesis for nano-electronic gate designs},
author = {D. A. Tran and Arnaud Virazel and Alberto Bosio and Luigi Dilillo and Patrick Girard and Serge Pravossoudovitch and Hans-Joachim Wunderlich},
year = {2010},
doi = {10.1109/TEST.2010.5699312},
url = {http://dx.doi.org/10.1109/TEST.2010.5699312},
researchr = {https://researchr.org/publication/TranVBDGPW10},
cites = {0},
citedby = {0},
pages = {820},
booktitle = {2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010},
editor = {Ron Press and Erik H. Volkerink},
publisher = {IEEE},
isbn = {978-1-4244-7206-2},
}