The following publications are possibly variants of this publication:
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- A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line ArchitectureJinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang. jssc, 50(11):2635-2644, 2015. [doi]