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3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat)

Kazuo Tsutsui, Kuniyuki Kakushima, T. Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, I. Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, Toshiro Hiramoto, A. Ogura, Y. Numasawa, Ichiro Omura, H. Ohashi, Hiroshi Iwai. 3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 1137-1140, IEEE, 2017. [doi]

Authors

Kazuo Tsutsui

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Kuniyuki Kakushima

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T. Hoshii

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A. Nakajima

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Shinichi Nishizawa

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Hitoshi Wakabayashi

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I. Muneta

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K. Sato

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Tomoko Matsudai

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Wataru Saito

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Takuya Saraya

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K. Itou

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M. Fukui

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S. Suzuki

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M. Kobayashi

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T. Takakura

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Toshiro Hiramoto

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A. Ogura

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Y. Numasawa

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Ichiro Omura

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H. Ohashi

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Hiroshi Iwai

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