3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat)

Kazuo Tsutsui, Kuniyuki Kakushima, T. Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, I. Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, M. Kobayashi, T. Takakura, Toshiro Hiramoto, A. Ogura, Y. Numasawa, Ichiro Omura, H. Ohashi, Hiroshi Iwai. 3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). In Yajie Qin, Zhiliang Hong, Ting-Ao Tang, editors, 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017. pages 1137-1140, IEEE, 2017. [doi]

@inproceedings{TsutsuiKHNNWMSM17,
  title = {3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat)},
  author = {Kazuo Tsutsui and Kuniyuki Kakushima and T. Hoshii and A. Nakajima and Shinichi Nishizawa and Hitoshi Wakabayashi and I. Muneta and K. Sato and Tomoko Matsudai and Wataru Saito and Takuya Saraya and K. Itou and M. Fukui and S. Suzuki and M. Kobayashi and T. Takakura and Toshiro Hiramoto and A. Ogura and Y. Numasawa and Ichiro Omura and H. Ohashi and Hiroshi Iwai},
  year = {2017},
  doi = {10.1109/ASICON.2017.8252681},
  url = {https://doi.org/10.1109/ASICON.2017.8252681},
  researchr = {https://researchr.org/publication/TsutsuiKHNNWMSM17},
  cites = {0},
  citedby = {0},
  pages = {1137-1140},
  booktitle = {12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017},
  editor = {Yajie Qin and Zhiliang Hong and Ting-Ao Tang},
  publisher = {IEEE},
  isbn = {978-1-5090-6625-4},
}