The following publications are possibly variants of this publication:
- Timing Error Tolerance in Pipeline Based Core DesignsStefanos Valadimas, Angela Arapoyanni. pci 2014: 1-6 [doi]
- Cost and power efficient timing error tolerance in flip-flop based microprocessor coresStefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni. ets 2012: 1-6 [doi]
- Timing Error Tolerance in Small Core Designs for SoC ApplicationsStefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni. TC, 65(2):654-663, 2016. [doi]
- Single event upset tolerance in flip-flop based microprocessor coresStefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans. dft 2012: 79-84 [doi]