Abstract is missing.
- Modeling SRAM start-up behavior for Physical Unclonable FunctionsMafalda Cortez, Apurva Dargar, Said Hamdioui, Geert Jan Schrijen. 1-6 [doi]
- Parametric counterfeit IC detection via Support Vector MachinesKe Huang, John M. Carulli Jr., Yiorgos Makris. 7-12 [doi]
- Path-delay fingerprinting for identification of recovered ICsXuehui Zhang, Kan Xiao, Mohammad Tehranipoor. 13-18 [doi]
- Using partial masking in X-chains to increase output compaction for an X-canceling MISRAsad Amin Bawa, Muhammad Tauseef Rab, Nur A. Touba. 19-24 [doi]
- On the development of Software-Based Self-Test methods for VLIW processorsDavide Sabena, Matteo Sonza Reorda, Luca Sterpone. 25-30 [doi]
- Low pin count DfT technique for RFID ICsMarcelo de Souza Moraes, Marcos Barcellos Hervé, Marcelo Lubaszewski. 31-36 [doi]
- Generation and compaction of mixed broadside and skewed-load n-detection test sets for transition faultsIrith Pomeranz. 37-42 [doi]
- A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structuresJean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede. 43-48 [doi]
- #SAT-based vulnerability analysis of security components - A case studyLinus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker. 49-54 [doi]
- Software exploitable hardware Trojans in embedded processorXinmu Wang, Tatini Mal-Sarkar, Aswin Raghav Krishna, Seetharam Narasimhan, Swarup Bhunia. 55-58 [doi]
- Minimization of Trojan footprint by reducing Delay/Area impactMehryar Rahmatian, Hessam Kooti, Ian G. Harris, Elaheh Bozorgzadeh. 59-62 [doi]
- Designing and implementing a Malicious 8051 processorJuan Carlos Martinez Santos, Yunsi Fei. 63-66 [doi]
- On the design of two single event tolerant slave latches for scan delay testingYang Lu, Fabrizio Lombardi, Salvatore Pontarelli, Marco Ottavi. 67-72 [doi]
- Hardening a memory cell for low power operation by gate leakage reductionJianping Gong, Yong-Bin Kim, Fabrizio Lombardi, Jie Han. 73-78 [doi]
- Single event upset tolerance in flip-flop based microprocessor coresStefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans. 79-84 [doi]
- An on-line soft error mitigation technique for control logic of VLIW processorsAlireza Rohani, Hans G. Kerkhoff. 85-91 [doi]
- Exploring hardware transaction processing for reliable computing in chip-multiprocessors against soft errorsChuanlei Zheng, Parijat Shukla, Shuai Wang, Jie S. Hu. 92-97 [doi]
- Amalgamated q-ary codes for multi-level flash memoriesYifat Manzor, Osnat Keren. 98-103 [doi]
- Accurate calculation of SET propagation probability for hardeningSreenivas Gangadhar, Spyros Tragoudas. 104-108 [doi]
- Transient pulse propagation using the Weibull distribution functionAdam Watkins, Spyros Tragoudas. 109-114 [doi]
- Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAsCinzia Bernardeschi, Luca Cassano, Andrea Domenici, Luca Sterpone. 115-120 [doi]
- High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologiesCristiana Bolchini, Antonio Miele, Chiara Sandionigi, Marco Ottavi, Salvatore Pontarelli, Adelio Salsano, Cecilia Metra, Martin Omaña, Daniele Rossi, Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Simone Gerardin, M. Bagatin, Alessandro Paccagnella. 121-125 [doi]
- A systematic methodology to improve yield per area of highly-parallel CMPsDa Cheng, Sandeep K. Gupta. 126-133 [doi]
- On the multiple fault detection of a nano crossbarFabrizio Lombardi, Nohpill Park, Haider A. F. Almurib, T. Nandha Kumar. 134-139 [doi]
- Prediction of gate delay variation for CNFET under CNT density variationAli Arabi M. Shahi, Payman Zarkesh-Ha. 140-145 [doi]
- Built-in generation of multi-cycle broadside testsIrith Pomeranz. 146-151 [doi]
- Fast single-FPGA fault injection platformGabriel L. Nazar, Luigi Carro. 152-157 [doi]
- Incorporating parameter variations in BTI impact on nano-scale logical gates analysisSeyab Khan, Said Hamdioui, Halil Kukner, Praveen Raghavan, Francky Catthoor. 158-163 [doi]
- Relating digital imager defect rates to pixel size, sensor area and ISOGlenn H. Chapman, Rohit Thomas, Israel Koren, Zahava Koren. 164-169 [doi]
- A low overhead built-in delay testing with voltage and frequency adaptation for variation resilienceKyu-Nam Shim, Jiang Hu. 170-177 [doi]
- Implementing defect tolerance in 3D-ICs by exploiting degrees of freedom in assemblyMuhammad Tauseef Rab, Asad Amin Bawa, Nur A. Touba. 178-181 [doi]
- Optimal choice of arithmetic compactors for mixed-signal systemsVadim Geurkov. 182-186 [doi]
- Dual-edge-triggered FF with timing error detection capabilityKazuteru Namba, Takashi Katagiri, Hideo Ito. 187-192 [doi]
- Improving small-delay fault coverage for on-chip delay measurementWenpo Zhang, Kazuteru Namba, Hideo Ito. 193-198 [doi]
- Faults affecting the control blocks of PV arrays and techniques for their concurrent detectionMartin Omaña, Daniele Rossi, G. Collepalumbo, Cecilia Metra, Fabrizio Lombardi. 199-204 [doi]
- Dirty data vulnerability mitigation by means of sharing management in cache coherence protocolsMohammad Maghsoudloo, Hamid R. Zarandi. 205-210 [doi]
- A mechanism to verify cache coherence transactions in multicore systemsRance Rodrigues, Israel Koren, Sandip Kundu. 211-216 [doi]
- Dependable routing in multi-chip NoC platforms for automotive applicationsTomohiro Yoneda, Masashi Imai. 217-224 [doi]
- A novel pseudonoise tester for transmission line fault location and identification using pseudorandom binary sequencesRichard A. Guinee. 225-232 [doi]
- Using the Berlekamp-Massey algorithm to obtain LFSR characteristic polynomials for TPGOscar Acevedo, Dimitri Kagaris. 233-238 [doi]
- Maintaining proximity to functional operation conditions under enhanced-scan tests based on functional broadside testsIrith Pomeranz. 239-244 [doi]