Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems

Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham. Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Transactions on Computers, 56(10):1401-1414, 2007. [doi]

Abstract

Abstract is missing.