Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks

Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan. Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. J. Low Power Electronics, 4(3):301-319, 2008. [doi]

@article{ViraraghavanAV08,
  title = {Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks},
  author = {Janakiraman Viraraghavan and Bharadwaj Amrutur and V. Visvanathan},
  year = {2008},
  doi = {10.1166/jolpe.2008.187},
  url = {http://dx.doi.org/10.1166/jolpe.2008.187},
  tags = {rule-based, logic},
  researchr = {https://researchr.org/publication/ViraraghavanAV08},
  cites = {0},
  citedby = {0},
  journal = {J. Low Power Electronics},
  volume = {4},
  number = {3},
  pages = {301-319},
}