Bipolar transistor epilayer design using the MAIDS mixed-level simulator

Leo C. N. de Vreede, Henk C. de Graaff, Joost A. Willemen, Wibo D. van Noort, Rik Jos, Lawrence E. Larson, Jan W. Slotboom, Joseph L. Tauritz. Bipolar transistor epilayer design using the MAIDS mixed-level simulator. J. Solid-State Circuits, 34(9):1331-1338, 1999. [doi]

Abstract

Abstract is missing.