Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab. Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. In Ron Press, Erik H. Volkerink, editors, 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010. pages 114-123, IEEE, 2010. [doi]
@inproceedings{WaayersMLK10,
title = {Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains},
author = {Tom Waayers and Richard Morren and Xijiang Lin and Mark Kassab},
year = {2010},
doi = {10.1109/TEST.2010.5699211},
url = {http://dx.doi.org/10.1109/TEST.2010.5699211},
researchr = {https://researchr.org/publication/WaayersMLK10},
cites = {0},
citedby = {0},
pages = {114-123},
booktitle = {2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010},
editor = {Ron Press and Erik H. Volkerink},
publisher = {IEEE},
isbn = {978-1-4244-7206-2},
}