Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains - researchr publication related

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Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab. Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. In Ron Press, Erik H. Volkerink, editors, 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010. pages 114-123, IEEE, 2010. [doi]

The following publications are possibly variants of this publication:

Architecture for Reliable Scan-Dump in the Presence of Multiple Asynchronous Clock Domains in FPGA SoCsAmitava Majumdar, Balakrishna Jayadev, Da Cheng, Albert Lin. ats 2017: 139-144 [doi]

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