Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs

Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty. Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs. IEEE Trans. on CAD of Integrated Circuits and Systems, 36(8):1406-1419, 2017. [doi]

@article{WangLKC17,
  title = {Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs},
  author = {Ran Wang and Zipeng Li and Sukeshwar Kannan and Krishnendu Chakrabarty},
  year = {2017},
  doi = {10.1109/TCAD.2016.2629422},
  url = {https://doi.org/10.1109/TCAD.2016.2629422},
  researchr = {https://researchr.org/publication/WangLKC17},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {36},
  number = {8},
  pages = {1406-1419},
}