Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. On automatic-verification pattern generation for SoC withport-order fault model. IEEE Trans. on CAD of Integrated Circuits and Systems, 21(4):466-479, 2002. [doi]
@article{WangTJ02,
title = {On automatic-verification pattern generation for SoC withport-order fault model},
author = {Chun-Yao Wang and Shing-Wu Tung and Jing-Yang Jou},
year = {2002},
doi = {10.1109/43.992770},
url = {http://doi.ieeecomputersociety.org/10.1109/43.992770},
researchr = {https://researchr.org/publication/WangTJ02},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {21},
number = {4},
pages = {466-479},
}