The following publications are possibly variants of this publication:
- An automorphic approach to verification pattern generation for SoC design verification using port-order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. tcad, 21(10):1225-1232, 2002. [doi]
- On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. hldvt 2001: 145-150 [doi]
- Automatic interconnection rectification for SoC design verification based on the port order fault modelChun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou. tcad, 22(1):104-114, 2003. [doi]