The following publications are possibly variants of this publication:
- Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technologyPengcheng Huang, Shuming Chen, Jianjun Chen. chinaf, 59(4), 2016. [doi]
- An SEU-Resilient SRAM Bitcell in 65-nm CMOS TechnologyQingyu Chen, Haibin Wang, Li Chen, Lixiang Li, Xing Zhao, Rui Liu, Mo Chen, Xuantian Li. et, 32(3):385-391, 2016. [doi]