The following publications are possibly variants of this publication:
- Reducing leakage in a high-performance deep-submicron instruction cacheMichael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy, T. N. Vijaykumar. tvlsi, 9(1):77-89, 2001. [doi]
- dd: a circuit technique to reduce leakage in deep-submicron cache memoriesMichael D. Powell, Se-Hyun Yang, Babak Falsafi, Kaushik Roy 0001, T. N. Vijaykumar. islped 2000: 90-95 [doi]
- Leakage Current in Deep-Submicron CMOS CircuitsKaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand. jcsc, 11(6):575-600, 2002. [doi]
- O:::2:::ABA: a novel high-performance predictable circuit architecture for the deep submicron eraYonghee Im, Kaushik Roy. tvlsi, 10(3):221-229, 2002. [doi]