A low power NoC router using the marching memory through type

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura. A low power NoC router using the marching memory through type. In 2014 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVII, Yokohama, Japan, April 14-16, 2014. pages 1-3, IEEE, 2014. [doi]

@inproceedings{YasudoKANWOSN14-0,
  title = {A low power NoC router using the marching memory through type},
  author = {Ryota Yasudo and Takahiro Kagami and Hideharu Amano and Yasunobu Nakase and Masashi Watanabe and Tsukasa Oishi and Toru Shimizu and Tadao Nakamura},
  year = {2014},
  doi = {10.1109/CoolChips.2014.6842960},
  url = {http://dx.doi.org/10.1109/CoolChips.2014.6842960},
  researchr = {https://researchr.org/publication/YasudoKANWOSN14-0},
  cites = {0},
  citedby = {0},
  pages = {1-3},
  booktitle = {2014 IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips XVII, Yokohama, Japan, April 14-16, 2014},
  publisher = {IEEE},
  isbn = {978-1-4799-3810-0},
}